RISC-V

Whats a good resource? Any guides or such you found particularly helpful? I'm only familiar with some basic x86 assembly, no SSE, AVX, etc. would it be "too much" to try and learn any Risc-V assembly?

Also, are there Risc-V devboards, and if so which ones are good, and what do you use yours for? Are they at an 8-bit microcontroller level, or ARM-running-Linux type beat? Asking the latter because it's always fun to have a real target when learning a new architecture.

Open-source RISC-V cores are increasingly demanded in domains like automotive and space, where achieving high instructions per cycle (IPC) through superscalar and out-of-order (OoO) execution is crucial. However, high-performance open-source RISC-V cores face adoption challenges: some (e.g. BOOM, Xiangshan) are developed in Chisel with limited support from industrial electronic design automation (EDA) tools. Others, like the XuanTie C910 core, use proprietary interfaces and protocols, including non-standard AXI protocol extensions, interrupts, and debug support.

In this work, we present a modified version of the OoO C910 core to achieve full RISC-V standard compliance in its debug, interrupt, and memory interfaces. We also introduce CVA6S+, an enhanced version of the dual-issue, industry-supported open-source CVA6 core. CVA6S+ achieves 34.4% performance improvement over CVA6 core.

We conduct a detailed performance, area, power, and energy analysis on the superscalar out-of-order C910, superscalar in-order CVA6S+ and vanilla, single-issue in-order CVA6, all implemented in a 22nm technology and integrated into Cheshire, an open-source modular SoC. We examine the performance and efficiency of different microarchitectures using the same ISA, SoC, and implementation with identical technology, tools, and methodologies. The area and performance rankings of CVA6, CVA6S+, and C910 follow expected trends: compared to the scalar CVA6, CVA6S+ shows an area increase of 6% and an IPC improvement of 34.4%, while C910 exhibits a 75% increase in area and a 119.5% improvement in IPC. However, efficiency analysis reveals that CVA6S+ leads in area efficiency (GOPS/mm2), while the C910 is highly competitive in energy efficiency (GOPS/W). This challenges the common belief that high performance in superscalar and out-of-order cores inherently comes at a significant cost in area and energy efficiency.

The KDE Frameworks are a set of 83 add-on libraries for programming with Qt. Part of it is also the syntax highlighting engine, used not only by KDE applications like Kate and KDevelop; but also by some others like Qt Creator.

Version 6.14 of KDE Framworks add support for RISC-V instructions/registers/… in GNU Assembler. Including some vendor-specific instructions.

Quick introduction to the RISC-V Vector spec. I thought some people might find this useful if they're trying to learn what SEW, ELEN, VLMAX, LMUL etc. mean.

The RISC-V vector C intrinsics provide users interfaces in the C language level to directly leverage the RISC-V "V" extension (RISC-V "V" Vector Extension, n.d.) (also abbreviated as "RVV"), with assistance from the compiler in handling instruction scheduling and register allocation. The intrinsics also aim to free users from responsibility of maintaining the correct configuration settings for the vector instruction executions. This document uses the term "RVV" as an abbreviation for the RISC-V "V" extension. This document uses the term "the RVV specification" to indicate the RISC-V "V" extension specification.

Earlier this month Canonical announced Ubuntu Linux support for the Orange Pi RV2 as a low-cost RISC-V developer board. The Orange Pi RV2 with eight RISC-V cores and 8GB of RAM costs just around $64 USD. The price point and specs were interesting that I ordered one and have been running performance benchmarks on it since for seeing how capable this is as finally an interesting, low-cost and readily available RISC-V board.

direct YT link: https://www.youtube.com/watch?v=9s8hPmCZ0mk

Has anyone used such a system as a "daily driver"?

What do you need to do in order to boot a normal distro such as Debian or such? How does it stand from the perspective of user/software freedom? What sorts of proprietary sh#ts does it need to be usable? What sorts of compromises that may not be obvious at first glance?

Also how does it "feel" day to day?

The SG2044 is the successor of the SG2042, with the same 64 core count but 8 LPDDR5X channels, 80 PCIe gen 5 lanes, and improved clock speed.

From what I can find in articles and reddit it supposed to have a launch date of 2024, but its not available on the sophon website or any other.

I am starting to worry it has been silently canceled, so does anyone know what happend to it? And if it's still coming what the projected release date is now?

Merged on Friday for the nearly-over Linux 6.15 merge window were the RISC-V CPU architecture updates for this next kernel release.

RISC-V with Linux 6.15 brings build improvements thanks to a re-architecting of the Kconfig build system options around RISC-V for selecting sub-architecture features.

For the Linux 6.15 kernel with RISC-V there is also support for building relocatable non-MMU kernels, support for huge PFNMAPS to improve TLB utilization, support for runtime constants, new RISC-V instructions supported, and a variety of fixes.

cross-posted from: https://lemmy.zip/post/35528933

China is doubling down on the RISC-V architecture.

cross-posted from: https://lemmy.ml/post/28025426

The European Chips Act has set ambitious goals and its implementation is a significant pan-european effort. From an academic perspective, last year we published an open letter emphasizing the critical importance of open-source EDA for academia in Europe. We were excited and grateful to see that this initiative triggered the definition of a European roadmap in this area, and a matching Chips JU call for project funding. We believe that the projects funded by this call will have a significant impact. Moreover, we already see rising interest from many EU stakeholders, with increasing investments into open-source chip design, especially in open source IP development (e.g. RISC-V cores), and open source EDA tools.

One additional critical barrier remains toward the end-goal of building real open-source chips, especially for prototyping and education: namely, streamlining the access to open source chip production facilities (foundries) is essential. Programs like ChipIgnite, Tiny Tapeout and IHP’s open source program have become “guiding stars” that demonstrate that everyone with a computer can build chips. We believe that having low-cost, regular and easy access to chip production is critical to create excitement and build up expertise, widening the pool of chip designers with tape-out experience: a true silicon democratization and a further de-mystification of chip design.

The CPU seems similar to the spacemit k1, but apparently there is no information about it. Too cheapt for rvv extensions?

In Europe 8GB version for less than 60€

cross-posted from: https://lemmy.world/post/26398664